The invention relates, in general, to non-volatile memory devices and, more particularly, to a non-volatile memory device and a method of fabricating the same, in which a floating gate having an increased surface area can be formed by employing an Advanced Self-Aligned Shallow Trench Isolation (ASA-STI) process.
A general non-volatile memory device is adapted to store data by using a program or erasure operation for injecting or discharging electrons into or from a floating gate through Fowler-Nordheim (F-N) tunneling. As described above, the non-volatile memory device necessarily requires floating gates, which are isolated from one another on an element basis, in order to store information.
The conventional isolated floating gate is formed by laminating first and second polysilicon layers between isolation layers. In this case, the second polysilicon layer must be formed thickly by taking the coupling ratio of a cell into consideration. However, if the thickness of the second polysilicon layer is too thick, the etch thickness of the patterning process increases, resulting in residual polysilicon. Thus, a problem arises because the operation of the device is adversely affected. In order to solve the problem, it is advantageous to reduce the thickness of the second polysilicon layer. However, there are another problems due to the coupling ratio of the cell.
In order to solve the problem, an ASA-STI process for performing primary patterning of the floating gate and the formation of trenches at a time has been employed. The process can solve an overlap problem between the floating gate and the isolation region, but the surface area of the floating gate is limited because the size of the polysilicon layer of the floating gate is determined by the isolation region.
Due to this, the coupling ratio decreases, and the isolation layer between the floating gates is removed because of degraded cycling characteristics. Accordingly, there is a limit to the lowering of the Effective Field Height (EFH).